Duration: 36 months
Several space-related technologies like Satellite-as-a-Service and Ground Station-as-a-Service or Embodied Intelligence for Space Transportation for both Launch Vehicles and In-Space Transportation Vehicles will require a large number of flexible, high-performance and low-cost computing platforms, likely decentralized in many peripheral subsystems. To achieve these requirements, integrated circuits for space applications shall be produced by following the very same design and production flow as commercial systems: many System-on-Chip (SoC) will integrate modules designed in-house with other modules coming from third party entities, either in the form of Third-Party IP cores (3PIPs) or in the form of Commercial Off-the-Shelf (COTS) components. Moreover, the final fabrication of the silicon device will rely on outsourced foundries. While ensuring high-performance and reduced cost, such globalized design process exposes the obtained system to several security threats both at design time and at runtime. In particular, purchased IP cores may contain unwanted functionalities or the final produced integrated circuit may be maliciously modified. Such stealthy unwanted functionalities are known as Hardware Trojan Horses (HTHs).
In this research we will study to add to the system one or more Intelligent Security Checkers meant for monitoring the activity carried out by the microprocessor and to detect at runtime the activitation of HTHs. We will try to answer the question, whether it is possible to secure a microprocessor-based system with a low (or even null) overhead by modifying the architecture of the microprocessor itself and by enriching the SoC with security checkers. As a beneficial additional side-effect, such ISCs would also allow to detect anomalous behaviors due to random faults (e.g. Soft Errors in memories, SEUs in registers) instead of malicious attacks. Of course, it is mandatory for the introduced security checker not to interfere with the nominal functioning of the system, i.e., not to introduce working frequency slow-down, and to bring the smallest possible silicon area and power consumption overhead.
