Duration: 18 months
Radiation-induced single-event upsets (SEUs) in on-board computers can flip one bit and derail a mission, driving late redesigns, extra beam campaigns, and blanket safeguards that triple power and silicon area. Today, such weaknesses surface only after hardware is built, so engineers default to full Triple Modular Redundancy (TMR)—yet blanket TMR still leaves gaps in ECSS traceability and throttles performance.
TuentesFlow moves reliability assurance into the design phase by coupling RTL-level analysis with a live FPGA implementation, whether on the flight device or an ASIC surrogate. Each validation run quantifies Architectural and Program Vulnerability Factors through emulated fault injections, highlighting where to insert just-enough protection: selective duplication on critical paths, byte-level ECC for high-risk memories, data-flow monitors, and RTOS probes. Mitigation is applied only until required reliability metrics are met, keeping designs lighter, cooler, and faster while still achieving mission goals. Crucially, designers receive feedback on reliability continuously during the design phase, before committing to full integration and hardware builds.
Validation runs on an unmodified Microchip PolarFire whose debug fabric flips individual flip-flops and SRAM cells at full speed; millions of injections chart the fault landscape in hours, and the same bitstream can be irradiated in a neutron beam to anchor the model in physics. TuentesFlow’s analytics rank residual risk and export FMEDAs, single-point fault metrics and fault databases ready for Synopsys VC Formal, Z01X, and FSM, bridging low-level faults to ECSS evidence.
In an 18-month Early Technology Development activity, the project will advance from TRL 2 to TRL 4, delivering a validated toolchain that can cut logic and power overhead by up to 60 percent, trim beam-time needs, and give ESA primes, SMEs, and researchers a rapid, traceable path to radiation-robust electronics.
