Duration: 36 months
The recent successes of AI-based capabilities have created new opportunities in space exploration. In 2020, the first mission using Deep Learning AI Earth observation algorithms onboard Φ-Sat-1 was launched [1]. From that point, several hardware architectures have enabled AI onboard satellites: soft GPU, COTS processors, and systolic-arrays architectures [2-8]. Among the various European solutions, the most advanced technology is based on the 28nm FDSOI technology. However, this technology has certain limitations in terms of performance when compared to US competitors, such as the AMD VERSAL, which uses the 7nm FinFET technology node [9]. This project aims at overcoming flexibility and energy-efficiency current limitations, by paving the way to implementing an AI Engine IP core on ultra-deep sub-micron (UDSM) technology. The UDSM is a disruptive high-performance technology upcoming in the space industry and capable of increasing the energy efficiency of space components [10].
As an AI hardware accelerator core, we leverage a resource-optimized, energy-efficient Coarse-Grained Reconfigurable Array (CGRA) [11-12] alongside a RISC-V-based SmartDMA, orchestrating the memory transactions. Algorithm execution will comprise the deployment of the scheduling algorithm on the RISC-V CPU and the configuration of the CGRA processing core.
The project will deal with the system integration and verification in Hardware Description Language (HDL) of the AI Engine, its implementation and characterization with a 7nm USDM technology employing the radiation hardening by design concept. The AI Engine IP core will be exploitable as an IP/chiplet in complex payload data handling systems and aims to enrich the European library characterisation of USDM technology. This aligns with the ESA's Technology Strategy [13], and has already gained interest from the industry (NanoXplore [14]).
References
[1] G. Giuffrida, L. Fannuci, G. Meoni, M. Batič, L. Buckley, A. Dunne, C. van Dijk, M. Esposito, J. Hefele, N. Vercruyssen, G. Furano, M. Pastena and J. Aschbacher, "The Φ-Sat-1 Mission: The First On-Board Deep Neural Network Demonstrator for Satellite Earth Observation," IEEE Transactions on Geoscience and Remote Sensing, 2022, doi: 10.1109/TGRS.2021.3125567
[2] M. Monopoli, L. Zulberti, P. Nannipieri and L. Fanucci, "Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications," in 2023 European Data Handling & Data Processing Conference (EDHPC), Juan-Les-Pins, France, doi: 10.36227/techrxiv.24117456.v1
[3] P. Ghiglino, "AI/ML Inference Engine Software for High-Reliability applications on Space Qualifiable Hardware," in EDHPC 2023 - European Data Handling & Data Processing Conference, 2023. Available: https://indico.esa.int/event/445/contributions/8446/ [Accessed 16 11 2023]
[4] D. Gonzalez-Arjona, J. Ferre, A. Jiménez-Peralo, D. Fortun, D. Lo Presti and D. Gogu, "Analysis and Implementation of Space Avionics Co-Processor for Deep Learning Acceleration," in EDHPC 2023 - European Data Handling & Data Processing Conference, 2023. Available: https://indico.esa.int/event/445/contributions/8480/ [Accessed 16 11 2023]
[5] Teledyne e2v Semiconductors, "Embedded Deep Learning in Space : Artificial Intelligence with Qormino®," 2021. [Online]. Available: https://semiconductors.teledyneimaging.com/en/newsroom/deep-learning-ai… [Accessed 14 11 2023].
[6] A. Shaji , F. Tosetti, H. Badri, M. Varile, N. Alony, P. Aviely, R. Ginosar, S. Yasui and T. Kurahashi, "Machine Learning Space Applications using RC64 Rad Hard Manycore Processor," in 2023 European Data Handling & Data Processing Conference (EDHPC), 2023. Available: https://indico.esa.int/event/445/contributions/8459/ [Accessed 16 11 2023]
[7] L. Kosmidis, M. S. Bonet, I. Rodriguez-Ferrandez, J. Wolf and M. M. Trompouki , "The METASAT Hardware Platform: A High-Performance Multicore, AI SIMD and GPU RISC-V Platform for On-board Processing," in 2023 European Data Handling & Data Processing Conference (EDHPC), 2023. Available: https://indico.esa.int/event/445/contributions/8402/ [Accessed 16 11 2023]
[8] O. Dokianaki, V. Baumgarte, M. Syed, C. Papadas, T. Helfers, G. Dramitinos, T. Scholastique, M. Kogan, I. Saenger, S. Lacan, O. Markakis and L. Hili, "HPDP: Architecture and design flow: High performance data processor," in 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2017, doi: 10.1109/AHS.2017.8046360
[9] AMD Xilinx, "ACAP at the Edge with the Versal AI Edge Series," 2021. [Online]. Available: https://docs.xilinx.com/v/u/en-US/wp518-ai-edge-intro [Accessed 16 11 2023]
[10] T. Cui, Q. Xie, Y. Wang, S. Nazarian and M. Pedram, "7nm FinFET standard cell layout characterization and power density prediction in near- and super-threshold voltage regimes," International Green Computing Conference, Dallas, TX, USA, 2014, pp. 1-7, doi: 10.1109/IGCC.2014.7039170.
[11] B. Sutter, P. Raghavan and A. Lambrechts, "Coarse-Grained Reconfigurable Array Architectures," in Handbook of Signal Processing Systems, Springer, 2019, pp. doi: 10.1007/978-3-319-91734-4_12.
[12] L. Zulberti, M. Monopoli, P. Nannipieri and L. Fanucci, "Highly-Parameterised CGRA Architecture for Design Space Exploration of Machine Learning Applications Onboard Satellites," in 2023 European Data Handling & Data Processing Conference (EDHPC), Juan-Les-Pins, France, doi: 10.36227/techrxiv.24100671.v1
[13] European Space Agency, "ESA's Technology Strategy," September 2022. Available: https://esamultimedia.esa.int/docs/technology/ESA_Technology_Strategy_V… [Accessed 16 11 2023]
[14] A. Kilic and E. Lepape, "Advancing Toward 7nm FinFET Rad-Hard FPGA for Future Space Applications," in 2023 European Data Handling & Data Processing Conference (EDHPC), 2023. Available: https://indico.esa.int/event/445/contributions/8399/ [Accessed 16 11 2023]
