Investigating Hardware Security in next-generation Space RISC-V Processors

Hardware security is paramount for mission-critical space systems, particularly with the rise of shared computational platforms executing potentially untrusted third-party software. Such environments are highly vulnerable to hardware-level threats like Transient Execution Attacks (TEAs), such as Spectre and Meltdown, which can compromise sensitive data and jeopardize mission integrity. This proposal focuses on studying novel hardware-based countermeasures using the open RISC-V architecture to address these critical vulnerabilities directly at the architectural level. Our proposed hardware innovations include architectural modifications to enforce predictable microarchitectural states, inherently mitigating TEA risks, in a way that is comletely independent from SW and Operating System. By focusing solely on architectural hardening and hardware-based modification's, this work aims to significantly enhance the trustworthiness and fundamental security of modern space processors intended for deployment in highly available, demanding computational environments within space applications.