This study explores a new routing method for electronic circuits using stacked microvia interconnections, as well as a novel test method for its reliability screening. This challenging design is a precursor for PCB technology development compatible with advanced microprocessors (NG-Ultra, XARKU060, RTG4), packaging (PBGA and Commercial-Off-The-Shelf), high signal speed (15-28 Gbps), dense pitch (0.5-0.8 mm) and high number of inputs/outputs (1000-3000). High Density Interconnections are an enabling technology in other industry segments and this study provides the framework for spin-in to space applications, with key benefits for on-board computers and video processing units. Microvia technology is notorious for latent and intermittent open circuit failure due to weaknesses that are difficult to screen. The so-called "hidden reliability threat" led to a global industry alert [6], as well as from two prime satellite integrators. The general maturity of the technology was questioned following repeated failures after critical EEE parts were assembled. These problems have been prohibiting implementation of this promising technology in ESA projects. To address this issue, this study will develop a new capability test methodology to quantify the robustness and assess margin of the processes from the suppliers. This approach entails a step-wise reduction of microvia drill diameter, which is a technology driver that leads to improved functionality, but also decreased reliability. Moreover, the global performance standard [7] describes the lack of correlation data between existing microvia test methods. This study will generate this correlation data, which enables a common approach across various industrial market segments. Finally, the interest for a round robin campaign among a wider pool of PCB manufacturers is to set benchmarks from global state-of-the-art manufacturers, which enables spinning in capabilities from other industry segments.
