There is an increasing interest in using complex System-on-Chip (SoC) on-board spacecraft to allow high performance and flexibility. “Satellite as a service” is a new concept where a satellite can be reconfigured to new user needs throughout its lifetime or at different parts of the orbits, with different on-board processing (OBP) tasks. To enable fast, flexible sw reconfiguration of on-board systems, high-performance processors are needed. Several COTS SoC are being evaluated for use as high-performance processors in space. Automotive GPU (Graphics Processing Unit) devices developed for Advanced Driver Assistance Systems (ADAS) are shown to efficiently accelerate OBP in space applications. Since they are developed for automotive applications, they need to adhere to strict safety/QA standards; low-power; and high-performance – all of which have parallels to satellite on-board processing systems. The main difference is that they have been developed for lower radiation environments and thus in space they may suffer errors that cause a functional interrupt or result in data errors. Low-cost hardware fault-tolerance solutions for automotive GPUs have been proposed in the literature (see background), exploiting the inherent redundancy within these parallel processors, without the need of replicating the entire COTS device. Also, to ensure no errors occur in the payload data, special software-only techniques have been proposed to detect upsets and if necessary, reprocess the data to avoid error propagation. When applying these mitigation techniques, the architectural complexity and power consumption of the system will increase, making the adaption of COTS SoC technology increasingly difficult for space applications. In the proposed work, the existing automotive solutions will be adapted for use in space together with the proposal of new HW/SW concepts for the fault-tolerance of COTS SoC, without unacceptably increasing the complexity and power consumption of the system.
