One of the key features making a difference between the traditional Hi-Rel components and the COTS is the Radiation Hardness Assurance approach. In the RHA strategy, two main aspects need to be addressed: cumulative effects, and Single Event Effects (SEE). The objective of this proposal is focused on the latter. The sensitivity to destructive and non-destructive SEE of any electronic board will determine its reliability and availability, respectively. This suggested approach intends to improve these two RAMS disciplines from a pragmatic point of view. The core component of the proposed design is a microcontroller ( COTS device from Texas Instruments Enhanced Products, based on ARM Cortex core). There are some devices being tested for Latchup aiming at New Space Market, where the characterization through heavy ion testing typically only covers up to 43 MeV·cm2/mg. Since this threshold does not guarantee SEL immunity up to the ECSS threshold of 60 MeV·cm2/mg, a SEL tolerant architecture based on two microcontrollers running in parallel is proposed. Current consumption is continuously monitored in the active microcontroller, and in case an event is detected, it is power cycled and control is transferred to the backup microcontroller. Both microcontollers will run in hot redundancy and a FPGA (rad-tol and reliable device) will act as arbiter, taking in real time the decision of toggling the nominal processor, based on a series of control signals and the current monitoring. On the other hand, the behavior of this kind of devices in terms of non-destructive events (SEU/SEFI) is often unknown, since an exhaustive characterization of the device is a complex and time-consuming process. Consequently, an ad hoc characterization of a subset of the microcontroller blocks is proposed. Complementarily to the heavy ion testing, an option to be considered for the SEU/SEFI characterization could be focused pulsed laser, trying to establish correlation between both sources of results.
