Neural Network algorithms have shown amazing results in tasks like computer vision, automatic-speech recognition and sensor fusion, as well. Unfortunately, state of the art performances are reached only by complex models which cannot be executed on-board edge devices with limited hardware resources. Even in case of simpler models, usually the number of operations required to obtain a result makes the execution of these algorithms unfeasible for most application on embedded devices, especially in case of limited power consumption or computational power requirements. Recently, the diffusion of hardware accelerators such as Myriad2 by Intel Movidius makes the application of these algorithms feasible, offloading the CPU from the inference of the neural network. Unfortunately, COTS hardware accelerators such has Myriad2, offer limited support for the most used frameworks such as Caffe and Tensorflow and are optimized for a reduced set of tasks. On the other hand, these tools make the design of an application simpler and less error prone, with reduced time-to-market compared to FPGA or ASIC realizations which can be optimized in terms of performance given their greater flexibility. The aim of this work is to create a framework for the design of hardware accelerators for neural networks. In particular, the framework will output the VHDL/Verilog description of the hardware accelerator given the neural network model, using fixed point arithmetic, pruning of negligible parameters or operations, quantization applied to weights and inter-layer truncation in order to reduce power consumption, area and memory footprint. The framework will be configurable in order to get the best trade-off between timing, area and power performance, given a set of constraints. This tool will make the realization of hardware accelerators on ASIC or FPGA competitive in terms of time-to-market, design and testing efforts with respect to COTS hardware accelerators.
